In the integrated circuit (IC) industry, low cost and low power microcontroller units (MCUs) are generally designed and manufactured having an 8 bit architecture. In other words, the registers are configured in 8 bit segments (i.e., 8-bit or 16-bit registers) and the data busses that connect various peripherals and circuits within the microcontroller are 8 bits in width. Therefore, when an 8 bit microcontroller implements a stack data structure in internal or external memory for use during interrupt processing, data is written and read from the stack 1 byte at a time. For example, when an interrupt occurs, a microcontroller may push nine bytes sequentially to a stack data structure in a time serial manner via nine push operations in order to save the state of the microcontroller before processing the interrupt. In order to return, the state of the machine after the interrupt processing is complete, nine sequential pop operations are used to restore the state of the machine.
In recent years, microcontrollers have been used in applications that require significantly more processing power. In order to obtain greater processing power, 8 bit or byte wide microcontroller architectures are now being progressed to 16 bit software compatible architectures with 16 bit busing. In doing so, a 16 bit stack structure is typically created in internal or external memory to allow for interrupt processing. In this 16-bit architecture, the CPU is able to write two bytes (16 bits) to the stack structure with a single instruction. Therefore, while 8 bit stack structures would take nine operations to write nine bytes to the stack memory, a 16 bit stack will require only five operations to write nine bytes of memory to the stack (i.e., four 16-bit write operations and one byte write).
However, a 16 bit stack that is written with an odd number of bytes (e.g., nine bytes) will result in misalignment of the next push operation since the last of the nine bytes written to the stack will only use the low order byte of that last 16 bit position in the stack while the high order byte is the next available location in the stack. A subsequent push of information to this stack will result in some 16 bit values being written in to odd addresses of the stack instead of even addresses where the high and low bytes of the 16 bit words are mis-aligned (i.e., not located beginning at even addresses). In order to handle such misalignment, architectures typically access the 16 bit stack structure by performing individual byte reads where nine memory operations are still required to retrieve nine bytes of information off of the 16-bit stack. Therefore, the 16 bit stack structure still suffers from the same performance as the older 8 bit stack technology due to the misalignment of data during push and pop operations of odd numbers of bytes. In addition, while stack pushes that were aligned beginning at an even address could be read off the stack in five 16-bit reads, other pushes that were made in a mis-aligned manner (starting at an odd address) would require nine byte reads. Therefore, the initiation of an interrupt and the recovery from an interrupt could consume a different amount of CPU clocks cycles depending upon the circumstances and status of the stack. This would adversely affect a software engineer's ability to perform adequate cycle counting operations in order to develop efficient software code. Therefore, using byte access mechanisms into a 16 bit stack memory to handle mis-aligned data was not advantageous, and offered very little improvement over prior 8 bit structures.
In order to obtain approved performance for mis-aligned pushes to a 16 bit stack, engineers have attempted to develop custom memory arrays for embedded use. However, memory arrays for microcontroller applications are generated automatically by a computer tool whereby design times of microcontrollers and time to market are greatly improved. If custom memory array designs are needed to handle mis-aligned memory accesses, then time to market and the MCU design cycle time is adversely affected.
Therefore, a need exists in the industry for an effective way of implementing a 16 bit wide stack in an 8 bit microcontroller environment whereby mis-aligned pushes and pops can be accomplished in a uniform and short same time period, the same as aligned push and pop operations.